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EM250
4.6.2
Simulated EEPROM
The EmberZNet PRO stack reserves a section of Flash memory to provide Simulated EEPROM storage area for
stack and customer tokens. Therefore, the EM250 utilizes 8kB of upper Flash storage. This section of Flash is
only accessible when mapped to the Flash window in the data-side address space. Because the Flash cells are
qualified for up to 1,000 write cycles, the Simulated EEPROM implements an effective wear-leveling algorithm
which effectively extends the number of write cycles for individual tokens.
4.6.3
Flash Information Area (FIA)
The EM250 also includes a separate 1024-byte FIA that can be used for storage of data during manufacturing,
including serial numbers and calibration values. This area is mapped to the data side of the address space,
starting at address 0x5000. While this area can be read as individual bytes, it can only be written to one word
at a time, and may only be erased as a whole. Programming of this special Flash page can only be enabled
using the SIF interface to prevent accidental corruption or erasure. The EmberZNet PRO stack reserves a small
portion of this space for its own use, but the rest is available to the application.
4.6.4
RAM
The EM250 integrates 5kB of SRAM. Like the Flash memory, this RAM is also mapped to both the program and
data-side address spaces. On the program side, the RAM is mapped to the top 2.5k words of the program
address space. The program-side mapping of the RAM is used for code when writing to or erasing the Flash
memory. On the data side, the RAM is also mapped to the top of the address space, occupying the last 5kB, as
shown in Figure 3 and Figure 4.
Additionally, the EM250 supports a protection mechanism to prevent application code from overwriting system
data stored in the RAM. To enable this, the RAM is segmented into 32-byte sections, each with a configurable
bit that allows or denies write access when the EM250 is running in Application Mode. Read access is always
allowed to the entire RAM, and full access is always allowed when the EM250 is running in System Mode. The
EmberZNet PRO stack intelligently manages this protection mechanism to assist in tracking down many
common application errors.
4.6.5
Registers
Table 41 provides a short description of all application-accessible registers within the EM250. Complete
descriptions are provided at the end of each applicable Functional Description section. The registers are
mapped to the data-side address space starting at address 0x4000. These registers allow for the control and
configuration of the various peripherals and modules. The registers may only be accessed as whole word
quantities; attempts to access them as bytes may result in undefined behavior. There are additional registers
used by the EmberZNet PRO stack when the EM250 is running in System Mode, allowing for control of the MAC,
baseband, and other internal modules. These system registers are protected from being modified when the
EM250 is running in Application Mode.
4.7
4.8
Encryption Accelerator
The EM250 contains a hardware AES encryption engine that is attached to the CPU using a memory-mapped
interface. NIST-based CCM, CCM*, CBC-MAC, and CTR modes are implemented in hardware. These modes are
described in the IEEE 802.15.4-2003 specification, with the exception of CCM*, which is described in the
ZigBee Security Services Specification 1.0. The EmberZNet PRO stack implements a security API for
applications that require security at the application level.
nRESET Signal
When the asynchronous external reset signal, nRESET (Pin 13), is driven low for a time greater than 200ns, the
EM250 resets to its default state. An integrated glitch filter prevents noise from causing an inadvertent reset
to occur. If the EM250 is to be placed in a noisy environment, an external LC Filter or supervisory reset circuit
is recommended to guarantee the integrity of the reset signal.
120-0082-000V Rev 1.1
Page 22
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